library ieee;
use ieee.std_logic_1164.all;

entity testbench_fir_filter_n is
end testbench_fir_filter_n;

architecture test of testbench_fir_filter_n is

	constant N 		: integer := 16;
	constant PERIOD : time	  := 10 ns;

	--component fir_filter_n
	--	generic ( N : integer := 16);
	--	port (
	--		nreset_i	: in  std_logic;
	--		clk_i 		: in  std_logic;
	--		x_i   		: in  std_logic_vector(N-1 downto 0);
	--		y_o   		: out std_logic_vector(N-1 downto 0)
	--	);
	--end component;

	signal nreset	: std_logic;
	signal clk 		: std_logic;
	signal x   		: std_logic_vector(N-1 downto 0);
	signal y   		: std_logic_vector(N-1 downto 0);

begin

	fir_filter_n_inst : entity work.fir_filter_n(struc)
		generic map (
			N => N
		) port map (
			nreset_i =>	nreset,
			clk_i 	 =>	clk,	
			x_i   	 =>	x,	
			y_o   	 => y
		);

	gen_clk : process
	begin
		clk <= '0';
		wait for PERIOD/2;
		clk <= '1';
		wait for PERIOD/2;
	end process;

	gen_test : process
	begin
		wait for (PERIOD*4);

		nreset 	<= '0';

		wait for (PERIOD);

		nreset 	<= '1';
		x		<= X"0F0F";

		wait for (PERIOD);

		x		<= X"F0F0";

		wait for (PERIOD);

		x		<= X"0001";

		wait;
	end process;

end test;
